A novel technique for load frequency control of multi-area power systems

In this paper, an adaptive type-2 fuzzy controller is proposed to control the load frequency of a two-area power system based on descending gradient training and error back-propagation. The dynamics of the system are completely uncertain. The multilayer perceptron (MLP) artificial neural network structure is used to extract Jacobian and estimate the system model, and then, the estimated model is applied to the controller, online. A proportional–derivative (PD) controller is added to the type-2 fuzzy controller, which increases the stability and robustness of the system against disturbances. The adaptation, being real-time and independency of the system parameters are new features of the proposed controller. Carrying out simulations on New England 39-bus power system, the performance of the proposed controller is compared with the conventional PI, PID and internal model control based on PID (IMC-PID) controllers. Simulation results indicate that our proposed controller method outperforms the conventional controllers in terms of transient response and stability

Load frequency control for multi-area power systems : a new type-2 fuzzy approach based on Levenberg–Marquardt algorithm

In this study, a new fuzzy approach is proposed for load frequency control (LFC) of a multi-area power system. The main control system is constructed by use of interval type-2 fuzzy inference systems (IT2FIS) and fractional-order calculus. In designing the controller, there is no need for the system dynamics, therefore the system Jacobian is obtained by a multilayer perceptron neural network (MLP-NN). Uncertainties are modeled by IT2FIS, and for training fuzzy parameters, Levenberg Marquardt algorithm (LMA) is used, which is faster and more robust than gradient descent algorithm (GDA). The system stability is studied by Matignon’s stability method under time-varying disturbances. A comparison between the proposed controller with type-1 fuzzy controller on the New England 39-bus test system is also carried out. The simulations demonstrate the superiority of the designed controller

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications

Ultra-low power signal processor for biomedical applications

Recent developments in integrated circuit (IC) design technology enable us to realize the complicated applications and algorithms which were mainly implemented in software-based platform. In addition, the rapid advancements in the world of digital signal and image processing have simultaneously brought the newer and more efficient algorithms into existence. For example, the frequency-based image processing that was first relied on Fourier transform, has been gradually looked for another powerful transforms. They not only unmask the frequency components, but also provide the position of the frequency components such as Laplacian and Gaussian Pyramids (LP and GP) and wavelet transform. Going to more than one dimensional signal processing necessitates having the transform providing more information of the signal such as directionality. For instance, curvelet (for continuous signals) and Contourlet (for two dimensional (2D) discrete signals) transforms have been developed to address those issues. By tracking the time passed from Fourier transform to Contourlet transform which is almost 130-year-old journey, we have been able to access to more information, though the complexity is considerably increasing. Now, there are various mathematically complex algorithms developed to achieve the desired outcome in the areas like biomedical and mobile applications, coding, robotics, three dimensional (3D) graphics and so on. Many of the mentioned applications require to be implemented in hardware in order to have the real-time performance. Moreover, some needs to be ultra-low power to operate for a longer time, especially for biomedical applications in which both battery life and thermal energy transferred to body tissues are of great concerns. For instance, the online spike sorting DSP has been developed to do sorting on the signals (spike) recorded from a brain in a real time. Two requirements that should be always met are the real-time performance and the power density. The latter one is also very essential because the hardware implanted in a brain must avoid damaging brain tissue. So, the main bottlenecks of achieving ultra-low power signal and image processors for biomedical and Internet of thing (IoT) applications are memory and computational complexity. In the first part of this thesis, I propose architecture level contributions to achieve ultra-low power digital processor for biomedical and IoT applications. The proposed techniques reduce the power and area by addressing the area- and power-hungry components of such applications which are FIFOs and memory. The proposed techniques are 1- FIFO with error-reduced data compression (FERDC) and 2- FIFO with adaptive error reduced data compression (FAERDC). FERDC internal parameters are set in advance and it has less design complexity. Whereas in the latter one, the adaptive mechanism updates internal parameters with respect to input data pattern to reduce the output error and gain more power and area saving. FERDC and FAERDC can be generally applied to various digital signal and image processors and hardware accelerators because there is no assumption on which FERDC and FAERDC are proposed. FERDC has been extensively investigated using the various simulations to verify the functionality as well as power and area reduction. Then FAERDC along with a proposed extension method for filtering and a near-threshold operation have been proposed to design an ultra-low power Laplacian Pyramid (LP) engine as a popular hardware accelerator. The LP has been fabricated in 180 nm CMOS technology and its functionality is verified at 0.5 V. In the next part of this thesis, Contourlet transform (CT) which is a multiresolution image representation is studied. CT is one of the latest directional image transform whose hardware implementation has not been yet investigated. It consists of LP and directional filter bank (DFB). DFB is extracting the frequency components with respect to their directions. We have proposed the first hardware architecture of CT and studied the DFB in detail. The proposed architecture has been functionally verified through extensive simulation results. DFB is also a memory-intensive algorithm through which the whole input should be iteratively read, processed and stored back in the memory. The last part of this thesis is devoted to a real-time multi-channel spike sorting chip. Various techniques are proposed to design a 128-channel real-time spike sorting DSP operating at near-threshold (NT) voltage. The main contributions are categorized as architecture and circuit levels. We have proposed a new spike detector, feature extraction and training algorithms to improve the accuracy of clustering and then reduce the memory requirement in training and clustering parts. In order to further reduce the area to accommodate 128 channels as well as leakage power, a full custom 8T-cell SRAM is designed to operate in NT. An auto-biased bit-line keeper provides a reliable sensing margin at near- and sub-threshold operation so that a single power supply can be used for both the digital core and SRAM. The measurement results verify the chip functionality at 0.54 V with 0.175 μW/ch.Doctor of Philosophy (EEE

Online adaptive type-2 fuzzy logic control for load frequency of multi-area power system

info:eu-repo/semantics/publishe

An area- and power-efficient FIFO with error-reduced data compression for image/video processing

Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents a technique named FIFO with error-reduced data compression (FERDC) to reduce the FIFO size for various filters. The proposed FERDC significantly reduces the area and power consumption while keeping the error metrics such as mean square error (MSE) and peak signal to noise ratio (PSNR) in the acceptable range. Simulation results of a two dimensional wavelet filter shows that the proposed FERDC technique achieves the FIFO size reduction of up to 44.44% with PSNR values larger than 39 dB, which leads to the reduction of at least 31.6% in the dynamic power and 44.44% in the leakage power.Accepted versio

Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits

Real time spike detection is the first critical step to develop spike-sorting for integrated brain circuits interface applications. Nonlinear Energy Operator (NEO) and absolute thresholding have been widely used as the spike detection algorithms where NEO has a better performance measured by the probability of detection and false alarm. This paper proposes a hybrid spike detection algorithm incorporating both spike detection algorithms to reduce the power and to keep the detection rate the same as that of NEO. In the proposed algorithm, the absolute thresholding is performed first to detect a potential spike. Once a potential spike is detected, NEO is executed to check whether the detected spike by absolute thresholding is valid. Since NEO is conditionally conducted, this reduces the overall power consumption. The simulation shows that the proposed hybrid method improves the power consumption by 54.48% compared to NEO in 65 nm CMOS technology.Accepted versio

An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS

This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 μW/channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm2/channel, which allows 333 channels/mm2